UARTDMACR

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Interpret as UARTDMACR

DMA Control Register, UARTDMACR

RXDMAE	Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled.
TXDMAE	Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled.
DMAONERR	DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted.

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